ADZS-21469-EZLITE【PDF 52/62 页】KIT EVAL EZ LITE ADSP-21469

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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

OUTPUT DRIVE CURRENTS

Preliminary Technical Data

Figure 39 shows typical I-V characteristics for the output driv-

ers of the ADSP-2146x. The curves represent the current drive

INPUT

OR

1.5V

1.5V

capability of the output drivers as a function of output voltage.

12

10

8

OUTPUT

Figure 41. Voltage Reference Levels for AC Measurements

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 40 ). Figure 44 shows graphically

6

4

TBD

how output delays and holds vary with load capacitance. The

graphs of Figure 42 , Figure 43 , and Figure 44 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

2

12

0

0

50

100

150

200

250

10

Figure 39. Typical Drive at Junction Temperature

8

TEST CONDITIONS

The ac signal specifications (timing parameters) appear in

Table 16 on Page 24 through Table 47 on Page 50 . These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 40 .

Timing is measured on signals when they cross the 1.5 V level as

6

4

2

0

TBD

described in Figure 41 . All delays (in nanoseconds) are mea-

0

50

100

150

200

250

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

Figure 42. Typical Output Rise/Fall Time (20% to 80%,

V DD_EXT = Max)

TESTER PIN ELECTRONICS

50

12

V LOAD

T1

DUT

70

45

OUTPUT

10

4pF

50

2pF

400

0.5pF

ZO = 50

TD = 4.04

(impedance)

1.18 ns

8

6

TBD

4

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

2

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

0

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

0

50

100

150

200

250

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 43. Typical Output Rise/Fall Time (20% to 80%,

Figure 40. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Rev. PrC

| Page 52 of 62 | January 2009

V DD_EXT = Min)

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